Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with clock signal, and memory device and computer system using same

ABSTRACT

A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digital signal is stored in an associated storage circuit and defines a timing offset between the corresponding digital signal and the clock. The clock is output along with each digital signal having the timing offset defined by the corresponding phase command and the digital signals are captured responsive to the clock and evaluated to determine if each digital signal was successfully captured. A phase adjustment command adjusts the value of each phase command. These operations are repeated for a plurality of phase adjustment commands until respective final phase commands allowing all digital signals to be successfully captured is determined and stored in the storage circuits.

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor memoriesand other integrated circuit devices, and is directed, moreparticularly, to synchronizing digital signals being transferred overbuses interconnecting such devices.

BACKGROUND OF THE INVENTION

[0002] Conventional computer systems include a processor (not shown)coupled to a variety of memory devices, including read-only memories(“ROMs”) which traditionally store instructions for the processor, and asystem memory to which the processor may write data and from which theprocessor may read data. The processor may also communicate with anexternal cache memory, which is generally a static random access memory(“SRAM”). The processor also communicates with input devices, outputdevices, and data storage devices.

[0003] Processors generally operate at a relatively high speed.Processors such as the Pentium III® and Pentium 4® microprocessors arecurrently available that operate at clock speeds of at least 400 MHz.However, the remaining components of existing computer systems, with theexception of SRAM cache, are not capable of operating at the speed ofthe processor. For this reason, the system memory devices, as well asthe input devices, output devices, and data storage devices, are notcoupled directly to the processor bus. Instead, the system memorydevices are generally coupled to the processor bus through a memorycontroller, bus bridge or similar device, and the input devices, outputdevices, and data storage devices are coupled to the processor busthrough a bus bridge. The memory controller allows the system memorydevices to operate at a lower clock frequency that is substantiallylower than the clock frequency of the processor. Similarly, the busbridge allows the input devices, output devices, and data storagedevices to operate at a substantially lower frequency. Currently, forexample, a processor having a 1 GHz clock frequency may be mounted on amother board having a 133 MHz clock frequency for controlling the systemmemory devices and other components.

[0004] Access to system memory is a frequent operation for theprocessor. The time required for the processor, operating, for example,at 1 GHz, to read data from or write data to a system memory deviceoperating at, for example, 133 MHz, greatly slows the rate at which theprocessor is able to accomplish its operations. Thus, much effort hasbeen devoted to increasing the operating speed of system memory devices.

[0005] System memory devices are generally dynamic random accessmemories (“DRAMs”). Initially, DRAMs were asynchronous and thus did notoperate at even the clock speed of the motherboard. In fact, access toasynchronous DRAMs often required that wait states be generated to haltthe processor until the DRAM had completed a memory transfer. However,the operating speed of asynchronous DRAMs was successfully increasedthrough such innovations as burst and page mode DRAMs which did notrequire that an address be provided to the DRAM for each memory access.More recently, synchronous dynamic random access memories (“SDRAMs”)have been developed to allow the pipelined transfer of data at the clockspeed of the motherboard. However, even SDRAMs are incapable ofoperating at the clock speed of currently available processors. Thus,SDRAMs cannot be connected directly to the processor bus, but insteadmust interface with the processor bus through a memory controller, busbridge, or similar device. The disparity between the operating speed ofthe processor and the operating speed of SDRAMs continues to limit thespeed at which processors may complete operations requiring access tosystem memory.

[0006] A solution to this operating speed disparity has been proposed inthe form of a computer architecture known as a synchronous linkarchitecture. In the synchronous link architecture, the system memorymay be coupled to the processor either directly through the processorbus or through a memory controller. Rather than requiring that separateaddress and control signals be provided to the system memory,synchronous link memory devices receive command packets that includeboth control and address information. The synchronous link memory devicethen outputs or receives data on a data bus that may be coupled directlyto the data bus portion of the processor bus.

[0007] An example of a computer system 10 using the synchronous linkarchitecture is shown in FIG. 1. The computer system 10 includes aprocessor 12 having a processor bus 14 coupled through a memorycontroller 18 and system memory bus 23 to three packetized orsynchronous link dynamic random access memory (“SLDRAM”) devices 16 a-c.The computer system 10 also includes one or more input devices 20, suchas a keypad or a mouse, coupled to the processor 12 through a bus bridge22 and an expansion bus 24, such as an industry standard architecture(“ISA”) bus or a peripheral component interconnect (“PCI”) bus. Theinput devices 20 allow an operator or an electronic device to input datato the computer system 10. One or more output devices 30 are coupled tothe processor 12 to display or otherwise output data generated by theprocessor 12. The output devices 30 are coupled to the processor 12through the expansion bus 24, bus bridge 22 and processor bus 14.Examples of output devices 24 include printers and a video displayunits. One or more data storage devices 38 are coupled to the processor12 through the processor bus 14, bus bridge 22, and expansion bus 24 tostore data in or retrieve data from storage media (not shown). Examplesof storage devices 38 and storage media include fixed disk drives floppydisk drives, tape cassettes and compact-disk read-only memory drives.

[0008] In operation, the processor 12 sends a data transfer command viathe processor bus 14 to the memory controller 18, which, in turn,communicates with the memory devices 16 a-c via the system memory bus 23by sending the memory devices 16 a-c command packets that contain bothcontrol and address information. Data is coupled between the memorycontroller 18 and the memory devices 16 a-c through a data bus portionof the system memory bus 23. During a read operation, data istransferred from the SLDRAMs 16 a-c over the memory bus 23 to the memorycontroller 18 which, in turn, transfers the data over the processor 14to the processor 12. The processor 12 transfers write data over theprocessor bus 14 to the memory controller 18 which, in turn, transfersthe write data over the system memory bus 23 to the SLDRAMs 16 a-c.Although all the memory devices 16 a-c are coupled to the sameconductors of the system memory bus 23, only one memory device 16 a-c ata time reads or writes data, thus avoiding bus contention on the memorybus 23. Bus contention is avoided by each of the memory devices 16 a-con the system memory 22 having a unique identifier, and the commandpacket contains an identifying code that selects only one of thesecomponents.

[0009] The computer system 10 also includes a number of other componentsand signal lines that have been omitted from FIG. 1 in the interests ofbrevity. For example, as explained below, the memory devices 16 a-c alsoreceive a master clock signal to provide internal timing signals, a dataclock signal clocking data into and out of the memory device 16, and aFLAG signal signifying the start of a command packet.

[0010] A typical command packet CA<0:39> for an SLDRAM is shown in FIG.2 and is formed by 4 packet words CA<0:9>, each of which contains 10bits of data. As will be explained in more detail below, each packetword CA<0:9> is applied on a command-address bus CA including 10 linesCA0-CA9. In FIG. 2, the four packet words CA<0:9> comprising a commandpacket CA<0:39> are designated PW1-PW4. The first packet word PW₁contains 7 bits of data identifying the packetized DRAM 16 a-c that isthe intended recipient of the command packet. As explained below, eachof the packetized DRAMs is provided with a unique ID code that iscompared to the 7 ID bits in the first packet word PW₁. Thus, althoughall of the packetized DRAMs 16 a-c will receive the command packet, onlythe packetized DRAM 16 a-c having an ID code that matches the 7 ID bitsof the first packet word PW₁ will respond to the command packet.

[0011] The remaining 3 bits of the first packet word PW₁ as well as 3bits of the second packet word PW₂ comprise a 6 bit command. Typicalcommands are read and write in a variety of modes, such as accesses topages or banks of memory cells. The remaining 7 bits of the secondpacket word PW₂ and portions of the third and fourth packet words PW₃and PW₄ comprise a 20 bit address specifying a bank, row and columnaddress for a memory transfer or the start of a multiple bit memorytransfer. In one embodiment, the 20-bit address is divided into 3 bitsof bank address, 10 bits of row address, and 7 bits of column address.Although the command packet shown in FIG. 2 is composed of 4 packetwords PW1-PW4 each containing up to 10 bits, it will be understood thata command packet may contain a lesser or greater number of packet words,and each packet word may contain a lesser or greater number of bits.

[0012] The memory device 16 a is shown in block diagram form in FIG. 3.Each 10 of the memory devices 16 a-c includes a clock generator circuit40 that receives a command clock signal CCLK and generates a largenumber of other clock and timing signals to control the timing ofvarious operations in the memory device 16 a. The memory device 16 aalso includes a command buffer 46 and an address capture circuit 48which receive an internal clock signal ICLK, a command packet CA<0:9> ona 10 bit command-address bus CA, and a terminal 52 receiving a FLAGsignal. A memory controller (not shown) or other device normallytransmits the command packet CA<0:9> to the memory device 16 a insynchronism with the command clock signal CCLK. As explained above, thecommand packet CA<0:39>, which generally includes four 10-bit packetwords PW1-PW4, contains control and address information for each memorytransfer. The FLAG signal identifies the start of a command packet, andalso signals the start of an initialization sequence. The command buffer46 receives the command packet from the command-address bus CA, andcompares at least a portion of the command packet to identifying datafrom an ID register 56 to determine if the command packet is directed tothe memory device 16 a or some other memory device 16 b, c. If thecommand buffer 46 determines that the command is directed to the memorydevice 16 a, it then provides the command to a command decoder andsequencer 60. The command decoder and sequencer 60 generates a largenumber of internal control signals to control the operation of thememory device 16 a during a memory transfer.

[0013] The address capture circuit 48 also receives the command packetfrom the command-address bus CA and outputs a 20-bit addresscorresponding to the address information in the command packet. Theaddress is provided to an address sequencer 64, which generates acorresponding 3-bit bank address on bus 66, a 10-bit row address on bus68, and a 7-bit column address on bus 70. The row and column addressesare processed by row and column address paths, as will be described inmore detail below.

[0014] One of the problems of conventional DRAMs is their relatively lowspeed resulting from the time required to precharge and equilibratecircuitry in the DRAM array. The SLDRAM 16 a shown in FIG. 3 largelyavoids this problem by using a plurality of memory banks 80, in thiscase eight memory banks 80 a-h. After a read from one bank 80 a, thebank 80 a can be precharged while the remaining banks 80 b-h are beingaccessed. Each of the memory banks 80 a-h receives a row address from arespective row latch/decoder/driver 82 a-h. All of the rowlatch/decoder/drivers 82 a-h receive the same row address from apredecoder 84 which, in turn, receives a row address from either a rowaddress register 86 or a refresh counter 88 as determined by amultiplexer 90. However, only one of the row latch/decoder/drivers 82a-h is active at any one time as determined by bank control logic 94 asa function of a bank address from a bank address register 96.

[0015] The column address on bus 70 is applied to a column latch/decoder100, which supplies I/O gating signals to an I/O gating circuit 102. TheI/O gating circuit 102 interfaces with columns of the memory banks 80a-h through sense amplifiers 104. Data is coupled to or from the memorybanks 80 a-h through the sense amps 104 and I/O gating circuit 102 to adata path subsystem 108 which includes a read data path 110 and a writedata path 112. The read data path 110 includes a read latch 120 thatstores data from the I/O gating circuit 102.

[0016] In the memory device 16 a shown in FIG. 3, 64 bits of data arestored in the read latch 120. The read latch then provides four 16-bitdata words to an output multiplexer 122 that sequentially supplies eachof the 16-bit data words to a read FIFO buffer 124. Successive 16-bitdata words are clocked through the read FIFO buffer 124 in response to aclock signal RCLK generated by the clock generator 40. The FIFO buffer124 sequentially applies the 16-bit data words to a driver circuit 128which, in turn, applies the 16-bit data words to a data bus DQ formingpart of the processor bus 14 (see FIG. 1). The FIFO buffer 124 alsoapplies two data clock signals DCLK0 and DCLK1 to the driver circuit 128which, in turn, applies the data clock signals DCLK0 and DCLK1 onrespective data clock lines 132 and 133. The data clocks DCLK0 and DCLK1enable a device, such as the memory controller 18, reading data on thedata bus DQ to be synchronized with the data. Particular bits in thecommand portion of the command packet CA0-CA9 determine which of the twodata clocks DCLK0 and DCLK1 is applied by the driver circuit 128. Itshould be noted that the data clocks DCLK0 and DCLK1 are differentialclock signals, each including true and complementary signals, but forease of explanation, only one signal for each clock is illustrated anddescribed.

[0017] The write data path 112 includes a receiver buffer 140 coupled tothe data bus 130. The receiver buffer 140 sequentially applies 16-bitdata words from the data bus DQ to four input registers 142, each ofwhich is selectively enabled by a signal from a clock generator circuit144. The clock generator circuit 144 generates these enable signalsresponsive to the selected one of the data clock signals DCLK0 andDCLK1. The memory controller or processor determines which data clockDCLK0 or DCLK1 will be utilized during a write operation using thecommand portion of a command packet applied to the memory device 16 a.As with the command clock signal CCLK and command packet, the memorycontroller or other device (not shown) normally transmits the data tothe memory device 16 a in synchronism with the selected one of the dataclock signals DCLK0 and DCLK1. The clock generator 144 is programmedduring initialization to adjust the timing of the clock signal appliedto the input registers 142 relative to the selected one of the dataclock signals DCLK0 and DCLK1 so that the input registers 142 cancapture the write data at the proper times. In response to the selecteddata clock DCLK0 or DCLK1, the input registers 142 sequentially storefour 16-bit data words and combine them into one 64-bit data wordapplied to a write FIFO buffer 148. The write FIFO buffer 148 is clockedby a signal from the clock generator 144 and an internal write clockWCLK to sequentially apply 64-bit write data to a write latch and driver150. The write latch and driver 150 applies the 64-bit write data to oneof the memory banks 80 a-h through the I/O gating circuit 102 and thesense amplifiers 104.

[0018] As mentioned above, an important goal of the synchronous linkarchitecture is to allow data transfer between a processor or memorycontroller and a memory device to occur at a significantly faster rate.However, as the rate of data transfer increases, it becomes moredifficult to maintain synchronization of signals transmitted between thememory controller 18 and the memory device 16 a. For example, asmentioned above, the command packet CA<0:39> is normally transmittedfrom the memory controller 18 to the memory device 16 a in synchronismwith the command clock signal CCLK, and the read and write data arenormally transferred between the memory controller 18 and the memorydevice 16 a in synchronism with the selected one of the data clocksignals DCLK0 and DCLK1. However, because of unequal signal delays andother factors, the command packet CA<0:39> may not arrive at the memorydevice 16 a in synchronism with the command clock signal CCLK, and writeand read data may not arrive at the memory device 16 a and memorycontroller 18, respectively, in synchronism with the selected one of thedata clock signals DCLK0 and DCLK1. Moreover, even if these signals areactually coupled to the memory device 16 a and memory controller 18 insynchronism with each other, they may loose synchronism once they arecoupled to circuits within these respective devices. For example,internal signals require time to propagate to various circuitry in thememory device 16 a, differences in the lengths of signal routes cancause differences in the times at which signals reach the circuitry, anddifferences in capacitive loading of signal lines can also causedifferences in the times at which signals reach the circuitry. Thesedifferences in arrival times can become significant at high speeds ofoperation and eventually limit the operating speed of the memory devices16 a and memory controller 18.

[0019] The problems associated with varying arrival times areexacerbated as timing tolerances become more restricted with higher datatransfer rates. For example, if the internal clock ICLK derived from thecommand clock CCLK does not latch each of the packet words CA<0:9>comprising a command packet CA<0:39> at the proper time, errors in theoperation of the memory device may result. Similarly, data errors mayresult during write operations if internal signals developed responsiveto the data clocks DCLK0 and DCLK1 do not latch data applied on the databus DQ at the proper time. During read operations, data errors maylikewise result if internal signals in the memory controller 18developed responsive to the data clock signals DCLK0 and DCLK1 from thememory device 16 a do not latch read data applied on the data bus DQ atthe proper time. Moreover, even if these respective clocks are initiallysynchronized, this synchronism may be lost over time during normaloperation of the memory device 16 a. Loss in synchronism may result froma variety of factors, including temperature variations in theenvironment in which the memory device 16 a is operating, variations inthe supply voltage applied to the memory device, and drift in operatingparameters of components within the memory device.

[0020] One skilled in the art will understand that synchronization ofthe clock signals CCLK, DCLK0, and DCLK1 is being used to mean theadjusting of the timing of respective internal clock signals derivedfrom these respective external clock signals so the internal clocksignals can be used to latch corresponding digital signals at the propertimes. For example, the command clock signal CCLK is synchronized whenthe timing of the internal clock signal ICLK relative to the commandclock signal CCLK causes packet words CA<0:9> to be latched at theproper times.

[0021] To synchronize the command clock signals CCLK and the data clocksignals DCLK0 and DCLK1 during write data operations, the memorycontroller 18 applies a test bit pattern and (FIG. 1) places the memorydevice 16 a in a command and write data synchronization mode. During thesynchronization mode, synchronization circuitry within the memory device16 a (not shown in FIG. 3) detects the applied bit pattern, places thedevice in the synchronization mode, and thereafter generates thenecessary control signals to control components within the memory deviceto synchronize the clock signals CCLK, DCLK0, and DCLK1 from thecontroller 18. The data clock signals DCLK0 and DCLK1 must similarly besynchronized for read operations between the memory controller 18 andmemory device 16 a.

[0022] As mentioned above, an important goal of the synchronous linkarchitecture is to allow data transfer between a processor and a memorydevice to occur at a significantly faster rate. It should be noted thatthe phrase “data transfer” as used herein includes all digital signalstransferred to and from the memory device 16 a, and thus includessignals on the CA and DQ busses as well as the FLAG signal. As the datatransfer rate increases, it becomes more difficult to maintain therequired timing between signals transmitted between the memory device 16a and the memory controller 18. For example, as mentioned above, thecommand packet CA<0:39> is normally transmitted to the memory device 16a in synchronization with the command clock signal CCLK, and the data isnormally transmitted to the memory device 16 a in synchronization withthe selected one of the data clock signals DCLK0 and DCLK1. However,because of unequal signal delays and other factors, the command packetwords CA<0:9> may not arrive at the memory device 16 a insynchronization with the command clock signal CCLK, and the data packetwords may not arrive at the memory device 16 a in synchronization withthe selected data clock signal DCLK0 or DCLK1. Moreover, even if thesesignals are actually coupled to the memory device 16 a insynchronization with each other, this timing may be lost once they arecoupled to circuits within the memory device. For example, internalsignals require time to propagate to various circuitry in the memorydevice 16 a, differences in the lengths of signal routes can causedifferences in the times at which signals reach the circuitry, anddifferences in capacitive loading of signal lines can also causedifferences in the times at which signals reach the circuitry. Thesedifferences in arrival times can become significant at high datatransfer rates and eventually limit the operating speed of thepacketized memory devices.

[0023] The problems associated with varying arrival times areexacerbated as timing tolerances become more restricted at higher datatransfer rates. For example, if the internal clock ICLK derived from thecommand clock CCLK does not cause each of the packet words CA<0:9>comprising a command packet CA<0:39> to latch at the proper time, errorsin the operation of the memory device may result. Thus, the timing orphase shift of the internal clock signal ICLK relative to the commandclock signal CCLK must be adjusted such that the ICLK signal may beutilized to successfully latch each of the respective command signalsCA<0>-CA<9> comprising a packet word CA<0:9>. This is truenotwithstanding the varying arrival times of the respective commandsignals CA<0>-CA<9> within each packet word CA<0:9> relative to the ICLKsignal.

[0024] Thus, for each of the clock signals CCLK, DCLK0, and DCLK1 thephase shift of respective internal clock signals derived from theserespective external clock signals must be adjusted so the internal clocksignals can be used to latch corresponding packet words at optimumtimes. For example, the phase shift of the internal clock signal ICLKrelative to the command clock signal CCLK must be adjusted so that allcommand signals CA<0>-CA<9> in each packet word CA<0:9> are latched atthe optimum time.

[0025] As the data transfer rate increases, the duration for which eachsignal CA<0>-CA<9> in a packet word CA<0:9> is valid decreases by acorresponding amount, as will be understood by one skilled in the art.More specifically, the data window or “eye” DE for each of theDQ<0>-DQ<15> signals decreases at higher data transfer rates. Asunderstood by one skilled in the art, the data eye DE for each of theDQ<0>-DQ<9> signals defines the actual duration that each signal isvalid after timing skew of the signal is considered. The timing skew ofthe DQ<0>-DQ<9> signals arises from a variety of timing errors such asloading on the lines of the DQ bus and the physical lengths of suchlines. FIG. 4 is a timing diagram illustrating the data eyes DE for anumber of the DQ<0>-DQ<9> signals. The solid lines indicate the idealDQ<0>, DQ<1>, and DQ<9> signals, and the dashed lines indicate the worstcase potential time skew for each of these signals. The data eyes DE ofthe DQ<0>, DQ<1>, and DQ<9> signals are defined by time intervals t₀-t₃,t₁-t₄, and t₅-t₇, respectively.

[0026] As data eyes DE of the applied signals DQ<0>-DQ<9> decrease athigh data transfer rates, it is possible that one or more of thesesignals in each data packet word DQ<0:15> will have arrival times suchthat not all signals in a packet word are simultaneously valid at thememory device 16 a, and thus cannot be successfully captured by theinternal clock signal ICLK. For example, in FIG. 4, the data eye DE ofthe DQ<0> signal from times t₁-t₃ does not overlap the data eye of theDQ<15> signal from times t₅-t₇. In this situation, the signals DQ<0> andDQ<15> are not both valid at the memory device 16 a at the same time sothe packet word DQ<0:15> cannot be successfully captured responsive tothe RCLK signal. The transition of the RCLK signal at time t₂ couldsuccessfully capture the DQ<0> and DQ<1> signals, but not the DQ<15>signal, and, conversely, the transition of the RCLK signal at time t₆could successfully capture the DQ<15> signal but not the DQ<0> and DQ<1>signals, both of which have already gone invalid at time t₆.

[0027] There is a need for synchronizing respective data clock signalsand corresponding data packet signals during the transfer of read databetween packetized memory devices and a memory controller. Although theforegoing discussion is directed to synchronizing clock signals inpacketized memory devices like SLDRAMs, similar problems exist in othertypes of integrated circuits as well, including other types of memorydevices.

SUMMARY OF THE INVENTION

[0028] According to one aspect of the present invention, a methodadaptively adjusts respective timing offsets of a plurality of digitalsignals relative to a clock signal being output along with the digitalsignals to enable a circuit receiving the digital signals successfullyto each of the digital signals responsive to the clock signal. Themethod includes storing in a respective storage circuit associated witheach digital signal a corresponding phase command. The phase commanddefines a particular timing offset between the corresponding digitalsignal and the clock signal. The clock signal is output along with eachdigital signal having the timing offset defined by the correspondingphase command. The digital signals are captured responsive to the clocksignal and evaluated to determine if each digital signal wassuccessfully captured. A phase adjustment command is generated to adjustthe value of each phase command. The operations of outputting the clocksignal through generating a phase adjustment command are repeated for aplurality of phase adjustment commands for each digital signal. A phasecommand that causes the digital signal to be successfully captured isthen selected, and the selected phase command is stored in the storagecircuit associated with the digital signal.

[0029] According to another aspect of the present invention, a readsynchronization circuit adaptively adjusts respective timing offsets ofa plurality of digital signals applied on respective signal terminalsand an external data clock signal to enable an external device to latchthe digital signals responsive to the external data clock signal. Theread synchronization circuit includes a plurality of latch circuits,each latch circuit including an input, an output coupled to a respectivesignal terminal, and a clock terminal. Each latch circuit stores asignal applied on the input and providing the stored signal on thesignal terminal responsive to a clock signal applied on the clockterminal. A plurality of phase command registers store phase commandswith each register being associated with at least one of the latchcircuits.

[0030] A clock generation circuit is coupled to latch circuits and thephase command registers and generates a plurality of internal clocksignals and the external data clock signal responsive to a read clocksignal. Each internal clock signal and the external clock signal has arespective phase shift relative to the read clock signal. The clockgeneration circuit selects one of the internal clock signals for eachlatch circuit in response to the associated phase command and appliesthe selected internal clock signal to the clock terminal of the latchcircuit to place digital signals on the corresponding signal terminalwith a timing offset determined by the phase shift of the selectedinternal clock signal.

[0031] A control circuit is coupled to the clock generation circuit andthe phase command registers and operates in response to asynchronization command to apply synchronization digital signals on theinputs of the latch circuits and to adjust the respective timing offsetsbetween the external data clock signal and the synchronization digitalsignals output by each latch circuit by adjusting the respective valuesof the phase commands. The circuit stores final phase commands in eachphase command register that allow the synchronization digital signals tobe successfully captured responsive to the external data clock signal.The read synchronization circuit may be utilized in a variety ofdifferent types of integrated circuits, including packetized memorydevices such as SLDRAMs, nonpacketized devices such as double-data-ratesynchronous dynamic random access memories (DDR SDRAMs), and alternativememory architectures having alternative clocking topologies.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a block diagram of a conventional computer systemincluding a plurality of packetized memory devices.

[0033]FIG. 2 is diagram showing a typical command packet received by thepacketized memory devices of FIG. 1.

[0034]FIG. 3 is a block diagram of a conventional packetized memorydevice in the computer system of FIG. 1.

[0035]FIG. 4 is a timing diagram illustrating the effect of timing skewson capturing respective data signals on the data bus at high datatransfer rates.

[0036]FIG. 5 is block diagram of a read synchronization system for apacketized memory device according to one embodiment of the presentinvention.

[0037]FIG. 6 is a timing diagram illustrating the operation of thesystem of FIG. 5 in adjusting the respective timing offsets of severaldata bits relative to a data clock signal to allow the memory controller(FIG. 5) to successfully capture all data bits in response to the dataclock signal.

[0038]FIG. 7 is a functional block diagram illustrating a memory systemincluding components of the read synchronization system of FIG. 5according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0039]FIG. 5 is a functional block diagram of a read synchronizationsystem 400 including a memory controller 402 and packetized memorydevice 404 according to one embodiment of the present invention. Thememory controller 402 applies command packets CA<0:39> and FLAG bits tothe memory device 404 over the command-address bus CA and FLAG line,respectively, and transfers data packet words D<0:15> on the data busDQ. During read operations, the memory controller 402 clocks thereceived data packet words D<0:15> into the controller responsive to oneof the data clocks DCLK0 and DCLK1. Prior to performing read operations,the memory controller 402 places the memory device 404 in a readsynchronization mode of operation and adjusts the timing offset ofrespective bits DQ<0>-DQ<15> in the data packet words D<0:15> relativeto the data clock signals DCLK0 and DCLK1 to synchronize the data clocksignals for use during normal read operations, as will be explained inmore detail below.

[0040] One skilled in the art will understand that synchronization ofthe data clock signals DCLK0 and DCLK1 as described herein means theadjustment of the timing offset of respective bits D<0>-D<15> in thedata packet words D<0:15> relative to the data clock signals DCLK0 andDCLK1 such that the memory controller 402 can successfully capture thedata packet words D<0:15> responsive to the data clock signals DCLK0 andDCLK1, as will be discussed in more detail below. In the followingdescription, certain details are set forth to provide a sufficientunderstanding of the present invention. However, it will be clear to oneskilled in the art that the invention may be practiced without theseparticular details. In other instances, well-known circuits, controlsignals, timing protocols, and software operations have not been shownin detail in order to avoid unnecessarily obscuring the invention.

[0041] In the memory device 404, the command buffer and address capturecircuit 46 (FIG. 3) latches packet words CA<0:9> and FLAG bits appliedon the respective command-address bus CA and FLAG line as previouslydescribed with reference to FIG. 3. A command decoder and sequencer 408receives the latched command packet CA<0:39> and FLAG bits from thecommand buffer and address capture circuit 46 and generates a pluralityof control signals 410 to control the operation of various componentswithin the memory device 404 in response to the latched command packetCA<0:39> and FLAG signals. During the read synchronization mode ofoperation, the command decoder and sequencer 408 generates a phaseadjust command word PHADJCMD<0:Y> in response to a phase adjustmentcommand that is applied on the command-address bus CA and latched by thecommand buffer and address capture circuit 46, as will be described inmore detail below.

[0042] An up/down phase counter-controller 416 latches the phase adjustcommand word PHADJCMD from the command decoder and sequencer 408 andoperates in response to the latched phase adjust command word to developa phase command word CMDPH<0:3> and to store the developed phase commandword in one of a plurality of phase command registers 434A-P, as will beexplained in more detail below. The latched CMDPH<0:3> word stored inthe registers 434A-P are designated as phase command wordsCMDPH0<0:3>-CMDPH15<0:3>, respectively. A plurality of multiplexers436A-P receive the CMDPH0<0:3>-CMDPH15<0:3> words, respectively, storedin the registers 434A-P, and further receive a plurality of clocksignals 438A-N from a delay-locked loop circuit 418 on respectiveinputs. The delay-locked loop circuit 418 develops the plurality ofclock signals 438A-N in response to the RCLK signal, with the clocksignals 438A-N having phase shifts, designated φ₁-φ_(N), respectively,relative to the RCLK signal. In the embodiment of FIG. 6, thedelay-locked loop circuit 418 develops sixteen clock signals 434A-N andmaintains a phase shift of 180° between the clock signals 438A and 438N.A more detailed description of one embodiment of a programmable-delayclock generation circuit that may be used as the delay locked loopcircuit 418 is described in U.S. patent application Ser. No. 08/811,918to Manning, which is incorporated herein by reference.

[0043] Each multiplexer 436A-P provides one of the applied clock signals438A-N on an output in response to the phase command wordCMDPH0<0:3>-CMDPH15<0:3> applied from the corresponding register 434A-P.The clock signals output by the multiplexers 436A-P are designated dataread clocks DRCLK0-DRCLK15, respectively, and are applied to clockrespective read synchronization data bits RSDW<0>-RSDW<15> into aplurality of data latches 440A-P. A read data pattern generator 424generates the RSDW<0>-RSDW<15> bits, as will be discussed in more detailbelow. In response to the applied DRCLK0-DRCLK15 signals, the latches440A-P store the applied RSDW<0>-RSDW<15> bits, respectively, and applythe stored bits through corresponding buffers 442A-P as the data bitsD<0>-D<15> on the data bus DQ. The DRCLK0-DRCLK15 signals thus determinewhen each latch 440A-P places the corresponding RSDW<0>-RSDW<15> bitonto the corresponding line of the data bus DQ relative to transitionsof the RCLK signal. This is true because each DRCLK0-DRCLK15 signalcorresponds to one of the clock signals 438A-N selected by thecorresponding multiplexer 436A-P responsive to the appliedCMPDH0<0:3>-CMDPH15<0:3> word, and each clock signal 438A-N has adefined phase shift relative to the RCLK signal as previously described.The memory device 404 further includes a data clock driver circuit 446that generates the data clock signals DCLK0 and DCLK1 in response to theread clock signal RCLK. Although the two data clocks DCLK0, DCLK1 arediscussed in the described embodiments, only one data clock may be usedin an alternative embodiment as will be understood by those skilled inthe art.

[0044] During the read synchronization mode of operation, the read datapattern generator 424 generates successive 16-bit read synchronizationdata packet words RSDW<0:15>, with respective bits RSDW<0>-RSDW<15> ineach word being clocked into respective data latches 440A-P in responsethe DCLK0-DCLK15 signals. During normal read operations, the 16-bit datapacket words D<0:15> corresponding to the data being accessed aresuccessively output from the multiplexer 122 (FIG. 3) and are clockedinto the data latches 440A-P responsive to the DCLK0-DCLK15 signals andthereafter applied through the buffers 442A-P and onto the data bus DQ.For ease of explanation and clarity of description, FIG. 5 illustratesonly the read data pattern generator 424 and corresponding RSDW<0:15>words being applied to the latches 440A-P. The driver circuit 446outputs the DCLK0, DCLK1 signals along with the RSDW<0:15> words beingsuccessively placed on the data bus DQ during the read synchronizationmode and outputs the selected one of the DCLK0, DCLK1 signals along withthe 16-bit data packet words being successively placed on the data busDQ during the normal read mode. The read data pattern generator 424 maygenerate a variety of data patterns, and in one embodiment the read datapattern generator 424 generates a 15-bit repeating pseudo-random bitsequence as described in U.S. patent application Ser. No. 09/143,033entitled METHOD AND APPARATUS FOR RESYNCHRONIZING A PLURALITY OF CLOCKSIGNALS USED TO LATCH RESPECTIVE DIGITAL SIGNALS, AND MEMORY DEVICEUSING SAME, to Manning, which is incorporated herein by reference.

[0045] During the read synchronization mode of operation, the memorycontroller 402 sequentially latches data words D<0:15> applied on thedata bus DQ by the memory device 404 in response to the selected DCLK0,DCLK1 signal. For each bit in the latched D<0:15> words, the memorycontroller 402 executes a synchronization process to determine whetherthe latched bit D<0>-D<15> was successfully captured in response to theselected one of the DCLK0, DCLK1 signals. For example, the controllercan generate an expected value for the bit D<0>-D<15> and compare thelatched bit to the expected value. When the two bits are equal, thecontroller 402 determines the bit was successfully captured, andotherwise determines the capture was unsuccessful. The controller 402then sends a phase adjustment command to the memory device 404 over theCA bus. In response to the phase adjustment command, the device 404adjusts the timing offset between the selected DCLK0, DCLK1 signal andthe bit D<0:15> being synchronized, and thereafter once again determineswhether the bit is successfully captured.

[0046] The overall operation of the read synchronization system 400 insynchronizing the data clock signals DCLK0 and DCLK1 during the readsynchronization mode of operation will now be described in more detail.The memory controller 402 operates in the read synchronization mode inresponse to a predetermined condition. For example, the memorycontroller 402 may operate in the read synchronization mode of operationas part of an initialization and synchronization procedure during whichthe memory controller 402 also synchronizes the command clock signalCCLK and the data clock signals DCLK0 and DCLK1 during write operations,and further performs other functions in initializing the memory device404. Alternatively, the memory controller 402 may operate in the readsynchronization mode of operation after a predetermined time duringnormal operation of the memory controller and memory device 404 in orderto periodically resynchronize the data clock signals DCLK0 and DCLK1.

[0047] After commencing operation in the read synchronization mode ofoperation, the memory controller 402 applies phase adjustment commandsto the memory device 404. Each phase adjustment command includesinformation identifying a particular memory device 404 and a particularbit D<0>-D<15> that is to be synchronized. contains information that isutilized by the memory device 404 to adjust the value of the phasecommand word CMDPH<0:3> stored in a corresponding phase command register434A-P, as will be explained in more detail below. The phase adjustmentcommand also selects one of the DCLK0, DCLK1 signals with which eachD<0>-D<15> bit is to be synchronized. As previously mentioned, the valueof the CMDPH<0:3> word adjusts the timing offset between thecorresponding bit D<0>-D<15> and transitions of the selected data clocksignal DCLK0 and DCLK1, and in this way the memory controller 402utilizes the phase adjustment commands to adjust this offset for eachbit D<0>-D<15>.

[0048] The command buffer and address capture circuit 46 latches theapplied phase adjustment commands read in response to the ICLK signal aspreviously described with reference to FIG. 3, and outputs the latchedcommand to the command decoder and sequencer 408. The command decoderand sequencer 408 decodes the command portion of the applied phaseadjustment command and thereafter generates the control signals 410 toplace the memory device 404 in the read synchronization mode ofoperation. As part of placing the memory device 404 in the readsynchronization mode, the up/down phase counter-controller 416 storesinitial values for the CMDPH0-CMDPH15<0:15> words in the phase commandregisters 434A-P, and the read data pattern generator 424 beginssequentially applying the read synchronization data words RSDW<0:15> tothe data latches 440A-P. The command decoder and sequencer 408 alsogenerates the phase adjustment command word PHADJCMD<0:Y> in response tothe applied phase adjustment command from the controller 402.The valueof the generated phase adjustment command word PHADJCMD<0:Y> isdetermined by the value of the phase adjustment command, and in this waythe memory controller 402 controls the value of the phase adjustmentcommand word PHADJCMD<0:Y>. As previously mentioned, the PHADJ<0:N> wordcontains information identifying a “selected” bit, which corresponds tothe bit D<0>-D<15> on the data bus DQ that is being synchronized, andthe PHADJCMD<0:Y> word similarly contains information identifying theselected bit.

[0049] The developed PHADJCMD<0:Y> word is applied to thecounter-controller 416, which first examines the latched PHADJCMD<0:Y>word to determine the selected bit and thereafter reads the currentvalue of the phase command word CMDPH<0:3> stored in the phase commandregister 434A-P associated with the selected bit. For example, if thePHADJCMD<0:Y> word identifies the bit D<0>, the counter-controller 416reads the value of the CMDPH0<0:3> word stored in the phase commandregister 434A. After reading the value of CMDPH<0:3> word stored in theselected phase command register 434A-P, the counter-controller 416generates a new value for the CMDPH<0:3> word responsive to thePHADJCMD<0:Y>. For example, the PHADJCMD<0:Y> word may containinformation instructing the counter-controller 416 to increment ordecrement the value of the read CMDPH<0:3> word. Once thecounter-controller 416 has generated the new CMDPH<0:3> word, thecounter-controller 416 stores the new word in the appropriate phasecommand register 434A-P. For example, if bit D<0> is being synchronized,the counter-controller 416 stores the newly generated value for theCMDPH0<0:3> word in the register 434A.

[0050] The counter-controller 416 can, alternatively, simply store anupdated phase command word CMDPH<0:3> in the appropriate register 434A-Presponsive to the PHADJCMD<0:Y> word. In this way, thecounter-controller 416 need not first read the CMDPH<0:3> word stored inthe register 413A-P being updated. In another embodiment of the system400, the counter-controller 416 can simultaneously adjust the values ofthe CMDPH0<0:3>-CMDPH15<0:3> words stored in the registers 434A-P,respectively. In this embodiment, the PHADJCMD<0:Y> word includesinformation the counter-controller 416 uses in independently adjustingeach of the CMDPH0<0:3>-CMDPH15<0:3> words.

[0051] At this point, the read synchronization data words RSDW<0:15>generated by the pattern generator 424 are clocked into the data latches440A-P responsive to the clock signals DRCLK0-DRCLK15, respectively,with each of these clock signals having an offset relative to the RCLKsignal. As previously described, each multiplexer 436A-P outputs aselected one of the clock signals 438A-N as the correspondingDRCLK0-DRCLK15 signal, with the selected clock signal being determinedby the value of the CMDPH0-CMDPH15<0:3> word applied to the multiplexerfrom the corresponding phase command register 434A-P. Thus, the databits RSDW<0>-RSDW<15> are clocked out of the data latches 440A-P havingrespective timing offsets relative to the RCLK signal and thus relativeto the DCLK0, DCLK1 signals, with each timing offset being determined bythe value of the CMDPH0-CMDPH15<0:3> word store in the correspondingphase command register 434A-P.

[0052] At this point, in the memory controller 402 latches appliedD<0:15> words responsive to the selected DCLK0, DCLK1 signal, and thendetermines whether the bit D<0>-D<15> being synchronized in the latchedword was successfully captured. The memory controller 402 compares thelatched value of the bit D<0>-D<15> being synchronized applied data wordD<0:63> to the expected value for the bit and stores the result of thecomparison. The Memory controller 402 thereafter generates a secondphase adjustment command including an incremented phase value, andapplies this new command to the memory device 404. The command bufferand address capture circuit 46 once again latches the applied phaseadjustment command and outputs the latched command to the commanddecoder and sequencer 408. In response to the incremented phase value inthis new phase adjustment command, the command decoder and sequencer 408applies a new PHADJCMD<0:Y> word to the counter-controller 416 which, inturn, reads the current value of the selected CMDPH0<0:3>-CMDPH15<0:3>word and increments or decrements the current value to develop a newCMDPH0<0:3>-CMDPH<15> word. The counter-controller 416 then stores thenew value of the CMDPH0<0:3>-CMDPH<15> word in the correspondingregister 434A-P. At this point, the RSDW<0>-RSDW<15> bits from thepattern generator 424 are clocked into the data latches 440A-Presponsive to the clock signals DRCLK0-DRCLK15, respectively, with eachof these clock signals having an offset relative to the DCLK0, DCLK1signals as determined the current values of the CMDPH0<0:3>-CMDPH15<0:3>words. The RSDW<0:15> words are thus clocked out of the data latches440A-P as the data initialization packet words D<0:15> on the data busDQ, each bit D<0>-D<15> having a timing offset relative to the selectedDCLK0, DCLK1 signal with the selected bit D<0>-D<15> currently beingsynchronized having a new timing offset as determined by the new valueof the corresponding CMDPH0<0:3>-CMDPH<0:3> word.

[0053] The memory controller 402 once again captures from the data busDQ the data initialization packet words D<0:15> having the new timingoffset applied to the bit D<0>-D<15> being synchronized, compares thelatched value to an expected value, and stores the result of thiscomparison. The memory controller 402 continues adjusting the value ofthe phase adjustment command and applying the adjusted commands to thememory device 404 in order to adjust the timing offset between theselected D<0>-D<15> bit and the selected data clock signal DCLK0, DCLK1.As the memory controller 402 adjusts the values of the phase adjustmentcommands, the memory controller stores a number of comparison results,each comparison result value corresponding to a particular value of thephase adjustment command (i.e., a particular timing offset of theselected bit D<0>-D<15> relative to the selected DCLK0 and DCLK1signal). After a predetermined number of comparison results have beenstored, the memory controller 402 executes a phase selection procedureto select a final phase adjustment command from among the phaseadjustment commands that resulted in the successful capture of theselected bit D<0>-D<15> as indicated by the corresponding comparisonresult. In one embodiment, the memory controller 402 stores sixteencomparison results, each corresponding to one of sixteen values for thephase adjustment command, and selects the final phase adjustment commandfrom among the ones of the sixteen values that resulted in thesuccessful capture of the selected D<0>-D<15> bit. One procedure thatmay be executed by the control circuit 406 in determining the finalphase adjustment word PHADJ<0:4> is described in more detail in U.S.Pat. No. 5,953,284 to Baker et al., entitled METHOD AND APPARATUS FORADAPTIVELY ADJUSTING THE TIMING OF A CLOCK SIGNAL USED TO LATCH DIGITALSIGNALS, AND MEMORY DEVICE USING SAME, which issued Sep. 14, 1999 andwhich is incorporated herein by reference.

[0054] After selecting the desired one of the phase adjustment commands,the memory controller 402 applies the selected phase adjustment commandto the memory device 404. The command buffer and address capture circuit46 and command decoder and sequencer 408 in the memory device 404 thenoperate as previously described develop the selected PHADJCMD<0:Y> wordcorresponding to the selected phase adjustment command. Thecounter-controller 416 receives the selected PHADJCMD<0:Y> word, whichincludes information indicating that the word corresponds to the finalselected value for the corresponding bit D<0>-D<15>. In response to theselected PHADJCMD<0:Y> word, the counter-controller 416 operates aspreviously described to update the value of the CMDPH0<0:3>-CMDPH<0:3>word stored in the register 434A-P corresponding to the bit beingsynchronized to a final value as determined by the selectedPHADJCMD<0:Y> word. For example, if the D<0> bit is being synchronized,the counter-controller 416 sets the value of the CMDPH0<0:3> word storedin the register 434A to a final value as determined by the selectedPHADJCMD<0:Y> word.

[0055] Upon the final phase command word CMDPH0<0:3>-CMDPH15<0:3> beingstored in the corresponding register 434A-P, the corresponding clocksignal DRCLK0-DRCLK15 signal has a phase relative to the read clocksignal RCLK that is determined by the final phase command word, and thisphase is utilized during normal read operations of the memory device404. This final phase command word CMDPH0<0:3>-CMDPH15<0:3> defines thetiming offset between the selected DCLK0, DCLK1 signal and thecorresponding bit D<0>-D<15>. This timing offset is then used duringnormal read operations of the memory device 404 so that the memorycontroller 402 may successfully capture this bit in the data packetwords D<0:15> being transferred to the memory controller in response toread commands from the controller. The memory controller 402 controlcircuit 406 thereafter develops a data clock offset to edge align thesecond DCLK0, DCLK1 signal with the selected data clock signal. Thatenables the controller 402 to successfully capture data bits D<0>-D<15>responsive to either DCLK0, DCLK1 signal.

[0056] After synchronizing both DCLK0, DCLK1 signals for the selectedbit D<0>-D<15>, the memory controller 402 develops a new phaseadjustment command identifying the next bit D<0>-D<15> to besynchronized, and the memory controller 402 and memory device 404thereafter operate in the same way as just described to synchronize thenewly selected bit. The controller 402 and memory device 404 repeat thisprocess for each of the bits D<0>-D<15> to independently synchronizeeach bit with the DCLK0, DCLK1 signals. When each bit D<0>-D<15> hasbeen synchronized, the phase command registers 434A-P store final phasecommand values CMDPH0<0:3>-CMDPH15<0:3> to define the respective timingoffsets between the each bit D<0>-D<15> and the DCLK0, DCLK1 signals. Aswill be understood by those skilled in the art, the exact processexecuted in synchronizing each D<0>-D<15> bit may be varied. For exampleeach bit D<0>-D<15> may first be synchronized with the DCLK0 signal, andthen each. synchronized with the DCLK1 signal. Alternatively, a selectedD<0>-D<15> bit may be synchronized with the DCLK0 signal, then the nextselected bit synchronized with the DCLK0, signal, and so on sequentiallyfor all bits. In another process, respective D<0>-D<15> bits may beindependently synchronized with the DCLK0, signal in parallel. Otherprocesses and combinations of the described processes may be utilizedand will be well understood by those skilled in the art.

[0057] In another embodiment of the synchronization system 400 of FIG.5, the memory device 404 includes a shadow register 450, which isindicated with dotted lines, coupled between the counter-controller 416and the phase command registers 434A-P. The shadow register 450 storesall the current CMDPH0-15<0:3> words, and functions as a storage“pipeline” between the counter-controller 416 and the registers 434A-P.In the system 400, the phase command registers 434A-P will typically belocated near the data latches 440A-P and buffers 442A-P, which will allbe physically proximate the external data bus DQ terminals of the memorydevice 404. In contrast, the counter-controller 416 may not be locatedphysically near the registers 434A-P, thus causing the transfer ofCMDPH0-15<0:3> words between the registers and the counter-controller tobe slowed down due to the physical lengths of the data linesinterconnecting these two components, as will be appreciated by thoseskilled in the art. If the counter-controller 416 must wait until anupdated CMDPH0-15<0:3> word has been stored in the correspondingregister 434A-P, the operation of the system 400 may be slowed down dueto the delay in transferring the words between the counter-controllerand the registers. With the shadow register 450, the counter-controller416 can quickly update the value of one of the CMDPH0-15<0:3> wordsresponsive to a corresponding phase adjustment command wordPHADJCMD<0:Y> and thereafter begin processing a subsequent PHADJCMD<0:Y>word. The shadow register 450 thereafter transfers the updatedCMDPH0-15<0:3> word to the proper register 434A-P while thecounter-controller 416 is processing the subsequent command wordPHADJCMD<0:Y>.

[0058]FIG. 6 is a signal timing diagram that will be utilized toillustrate the relationship between the phase shift of theDRCLK0-DRCLK15 signals relative to the RCLK signal as defined by therespective CMDPH0<0:3>-CMDPH<15> words, and also illustrates thecorresponding timing offset between the DCLK0 signal and respective bitsD<0>-D<15> applied on the data bus DQ. In the example of FIG. 5, theDCLK0 signal, which is generated by the drivers 446 in response to theRCLK signal, has the same phase as the RCLK signal. FIG. 5 illustratesthe three different delayed read clock signals DRCLK0, DRCLK1, andDRCLK15 corresponding to values CMDPH0<0:3>, CMDPH1<0:3>, andCMDPH15<0:3> of the phase command word stored in the registers 434A,434B, and 434P, respectively. As shown, the DRCLK0 signal has a phaseshift φ₁ relative to the DCLK0 signal. When the DRCLK0 signal goes highat a time t₁, the corresponding data bit D<0> is placed on the data busDQ have a timing offset t_(off1) relative to the rising edge of DCLK0signal at a time t₀. As previously discussed, the data bit D<0> isoffset by the time t_(off1) to enable the memory controller 402 tosuccessfully latch the data bit in response to the DCLK0 signal.

[0059] In the second example of FIG. 5, the DRCLK1 signal correspondingto the CMDPH1<0:3> word has a phase shift φ₂ relative to the DCLK0signal, and the corresponding data bit D<1> has a timing offset t_(off2)relative to the rising edge of the DCLK0 signal at the time t₀. Thus, inthis example the data bit D<1> is applied on the data bus DQ at a timet₂ before the rising edge of the DCLK0 signal at the time t₀. The thirdexample illustrates the DRCLK15 signal having a phase shift φ₃ relativeto the DCLK0 signal, and the corresponding data D<15> has a timingoffset t_(off3) relative to the rising edge of the DCLK0 signal at thetime t₀. In this example, the data D<15> is applied on the data bus DQat a time t₃ before the rising edge of the DCLK0 signal at the time t₀.As illustrated by these examples, the phase command words CMDPH0<0:3>,CMDPH1<0:3>, and CMDPH15<0:3> are independently adjusted to thereby varythe phase shift of the DRCLK0-DRCLK15 signals relative to the DCLK0signal. As the respective phase shifts of the DRCLK0-DRCLK15 signals areadjusted relative to the DCLK0 signal, the timing offsets of therespective data bits D<0>-D<15> in each data packet D<0:15> applied onthe data bus DQ are adjusted relative to transitions of the DCLK0 signalby an amount corresponding to the adjusted phase shifts.

[0060] One skilled in the art will realize that the procedure executedby the control circuit 406 in synchronizing the data clock signalsDCLK0, DCLK1 may vary. For example, in the above-described procedure thecontrol circuit 406 captures only one data packet D<0:63> at each phaseof the DRCLK0-DRCLK15 signal corresponding to the bit D<0>-D<15> beingsynchronized. In another embodiment, the control circuit 406 may performa predetermined number of comparisons at each given phase of theDRCLK0-DRCLK15 signal and timing offset of the corresponding D<0>-D<15>bit relative to the data clocks DCLK0 and DCLK1. In this embodiment, thecontrol circuit 406 may, for example, control components of the memorycontroller 402 so that eight data packets D<0:63> are captured andcompared at each phase of the DRCLK0-DRCLK15 signals. When all eight ofthese comparisons indicate successful captures, the control circuit 406stores a “1” indicating successful data capture at this phase. However,if any of the comparisons at a given phase indicates an unsuccessfulcapture, the control circuit 406 stores a “0” indicating failure at thisphase. Once again, after sixteen, for example, results signals have beenstored, the control circuit 406 determines the final phase adjustmentword PHADJ<0:4> and transfers this word to the memory device 404. Thememory device 404 then operates as previously described, applying thecorresponding PHADJCMD<0:Y> word to the counter-controller 416 which, inturn, stores the final phase command word CMDPH0<0:3>-CMDPH15<0:3> inthe appropriate phase command register 434A-P to thereby set the finalphase of the corresponding DRCLK0-DRCLK15 signal being adjusted.

[0061] The overall operation of the read synchronization system 400 andgeneral operation of several components within that circuit have nowbeen described with reference to FIG. 4. More detailed circuitry forimplementing the components of the read synchronization system 400contained within the memory controller 402 and memory device 404 will beunderstood by those skilled in the art, and are not provided in moredetail to avoid unnecessarily obscuring the present invention. Severalof these components are described in more detail in U.S. Pat. No.6,029,250 to Keeth entitled METHOD AND APPARATUS FOR ADAPTIVELYADJUSTING THE TIMING OFFSET BETWEEN A CLOCK SIGNAL AND DIGITAL SIGNALSTRANSMITTED COINCIDENT WITH THAT CLOCK SIGNAL, AND MEMORY DEVICE ANDSYSTEM USING SAME, which is incorporated herein by reference. Inaddition, in addition to being used with a programmable delay circuit,such as the delay-locked loop 418, the present invention may be usedwith other circuits for adjusting the timing offset between electricalsignals, such as the command delay rings 506 a described in U.S. patentapplication. Ser. No. 09/201,519 to Keeth, entitled METHOD AND APPARATUSFOR HIGH SPEED DATA CAPTURE UTILIZING BIT-TO-BIT TIMING CORRECTION, ANDMEMORY DEVICE USING SAME, which was filed on Nov. 30, 1998 and which isincorporated herein by reference. Furthermore, as previously mentioned,the synchronization system 400 may be used in a variety of differenttypes of memory devices in addition to the SLDRAM devices describedherein, such as in RAMBUS type memory devices and in double-data-ratesynchronous dynamic random access memory devices (“DDR SDRAMs”). In DDRSDRAMs, the timing offsets of respective bits on the data bus DQ areadjusted with respect to a data strobe signal DQS, as will beappreciated by those skilled in the art.

[0062]FIG. 7 is a functional block diagram illustrating a memory system700 including memory devices 702, 704 that include read synchronizationcircuits 703, 705 according to another embodiment of the presentinvention. Each of the read synchronization circuits 703, 705 includescomponents (not shown) of the read synchronization system 400 of FIG. 5,as will be discussed in more detail below. In the memory system 700, aclock generator 706 generates a system read clock signal RCLK that isapplied to the memory devices 702, 704 and is applied to a memorycontroller 708. During a read operations, the memory device 702, 704being accessed supplies read data on a data bus DQ and the memorycontroller 708 latches the read data in response to the RCLK signal.During write operations, the memory controller 708 supplies write dataon the data bus DQ and applies a write clock signal WCLK to the memorydevices 702, 704 which, in turn, latch the write data in response to thewrite clock signal. The memory controller 708 applies command andaddress information to the memory devices 702, 704 over a command busCMD and also applies a command clock signal CCLK that the memory devicesutilize to latch the applied command and address information. Oneskilled in the art will appreciate that the command bus CMD may be amultiplexed bus including both command and address information when thememory devices 702, 704 are packetized type memory devices such asSLDRAMs. Alternatively, the command bus CMD may include separate commandand address busses when the memory devices 702, 704 are non packetizedtype memory devices such as a DDR SDRAM.

[0063] During normal write operations, the memory controller 708 appliesa write command on the CMD bus to the memory devices 702, 704 which, inturn, latch the write command in response to the CCLK signal alsoapplied by the memory controller. Each of the memory devices 702, 704decodes the latched command and determines whether it is the devicebeing accessed. The memory controller 708 supplies write data on the DQbus and the memory device 702, 704 being accessed latches the suppliedwrite data in response to the CCLK signal from the memory controller.During normal read operations, the memory controller 708 applies theread command on the CMD bus to the memory devices 702, 704 which, onceagain, latch and decode the read command. The memory device 702, 704being accessed thereafter supplies read data on the DQ bus and thememory controller 708 latches the read data in response to the RCLK thesignal from the clock generator 706. Each of the data bits on the DQ bushas a respective timing offset relative to the RCLK signal, with thetiming offsets being determined during a read synchronization mode ofoperation. The respective timing offsets allow the memory controller 708to successfully capture all read data bits supplied on the DQ bus duringnormal read operations. During the read synchronization mode ofoperation, the circuits 703, 705 operate in an analogous manner tocomponents of the read synchronization system 400 of FIG. 5. Suchoperation will be well understood by those skilled in the art in view ofthe previous detailed description of the read synchronization system 400of FIG. 5, and thus, for the sake of brevity, will not be described inmore detail. Briefly, for each data bit on the data bus DQ a phasecommand CMDPH is stored in corresponding phase command register434A-434P (see FIG. 5) to define the timing offset between the data bitand the RCLK signal.

[0064] It is to be understood that even though various embodiments andadvantages of the present invention have been set forth in the foregoingdescription, the above disclosure is illustrative only, and changes maybe made in detail, and yet remain within the broad principles of theinvention. For example, many of the components described above may beimplemented using either digital or analog circuitry, or a combinationof both, and also, where appropriate, may be realized through softwareexecuting on suitable processing circuitry. Therefore, the presentinvention is to be limited only by the appended claims.

1. A method of transferring digital signal packets out of a packetizedmemory device on a data bus, each digital signal packet including atleast one packet word including a plurality of digital signals that areapplied to respective latches in the packetized memory device, themethod comprising: placing the packetized memory device in asynchronization mode of operation; generating a data clock signalresponsive to a read clock signal and applying the data clock signal ona corresponding line of the data bus; generating a plurality of internalclock signals read clock signal, each internal clock signal having aphase shift relative to the data clock signal; storing for each digitalsignal a phase command in a corresponding storage circuit associatedwith the digital signal, the phase command having a value correspondingto one of the internal clock signals; placing each digital signal on acorresponding data bus line responsive to the internal clock signalcorresponding to the phase command stored in the associated storagecircuit; receiving a phase adjustment command corresponding to aparticular digital signal that is being synchronized, the phaseadjustment command containing adjustment information for the phasecommand associated with the digital signal; adjusting the value of thephase command stored in the storage circuit associated with the digitalsignal being synchronized responsive to the phase adjustment commanduntil the value of the phase command defines a timing offset between thedigital signal and the data clock that allows and external device tosuccessfully capture the digital signal responsive to the data clocksignal; and repeating the operations of placing each digital signal on acorresponding bus line to adjusting the value of the phase commandsignal for each digital signal in the packet word.
 2. The method ofclaim 1 wherein the values of the phase commands for all the digitalsignals are adjusted in parallel.
 3. The method of claim 1 whereinadjusting the value of the phase command stored in the storage circuitcomprises reading an initial value of the phase command from the storagecircuit, incrementing or decrementing the values of the initial phasecommand response to the phase or adjustment command, to generate a newphase command, and storing the new phase command in the storage circuit.4. The method of claim 1 wherein each storage circuit comprises aregister.
 5. The method of claim 1 wherein placing the packetized memorydevice in the synchronization mode comprises capturing a FLAG signal andgenerating a calibration signal when the FLAG signal has a predeterminedbinary value for two consecutive captures.
 6. The method of claim 1wherein adjusting the value of the phase command stored in the storagecircuit associated with the digital signal being synchronized comprises:repetitively placing digital signals having expected values onto thecorresponding data bus line; evaluating the digital signal capturedresponsive to the data clock signal to determine if captured digitalsignal has the expected value; identifying each phase command thatcaused the associated digital signal having the expected value to becaptured; selecting a phase command for each digital signal from one ofthe phases that caused the associated digital signal having the expectedvalue to be captured; and storing the selected phase command in thecorresponding register.
 7. The method of claim 6 wherein the operationsof evaluating the captured digital signal to determine if the storeddigital signal has the expected value through storing the selected phasecommand in the corresponding register are performed sequentially on eachof the digital signals to sequentially select a phase command associatedwith each digital signal.
 8. The method of claim 6 wherein evaluatingthe captured digital signal to determine if the digital signal has theexpected value comprises: capturing the digital signal responsive to thedata clock signal; generating expected values for the digital signalresponsive to the digital the values of the captured digital signal;capturing the digital signal responsive to the data clock signal; anddetermining that the digital signal was successfully captured when thevalues of the captured digital signal corresponds to the generatedexpected values for the digital signal.
 9. A method of adaptivelyadjusting respective timing offsets of a plurality of digital signalsrelative to a clock signal being output along with the digital signalsto enable a circuit receiving the digital signals successfully to eachof the digital signals responsive to the clock signal, the methodcomprising: storing in a respective storage circuit associated with eachdigital signal a corresponding phase command, the phase command defininga particular timing offset between the corresponding digital signal andthe clock signal; outputting the clock signal; outputting each digitalsignal having the timing offset defined by the corresponding phasecommand; capturing the digital signals responsive to the clock signal;evaluating the captured digital signals to determine if each digitalsignal was successfully captured; generating a phase adjustment commandto adjust the value of each phase command; repeating the operations ofoutputting the clock signal through generating a phase adjustmentcommand for a plurality of phase adjustment commands for each digitalsignal; selecting for each digital signal a phase command that causesthe digital signal to be successfully captured; and storing in thestorage circuit associated with each digital signal the correspondingselected phase command.
 10. The method of claim 9 wherein the operationsof outputting a clock signal through generating a phase adjustmentcommand are performed in parallel on all the digital signals.
 11. Themethod of claim 9 wherein generating a phase adjustment command toadjust the value of each phase command comprises reading an initialvalue of the phase command from the storage circuit, incrementing ordecrementing the values of the initial phase command response to thephase adjustment command, to generate a new phase command, and storingthe new phase command in the storage circuit.
 12. The method of claim 9wherein each storage circuit comprises a register.
 13. The method ofclaim 9 wherein the clock signal corresponds to a data clock signaloutput from a packetized memory device and each digital signalcorresponds to a data signal applied on a data bus of the packetizedmemory device.
 14. The method of claim 12 wherein outputting eachdigital signal having the timing offset defined by the correspondingphase command comprises outputting a repeating 15 bit pseudo-random bitsequence of “1111010110001000” for each digital signal, with the timingoffset of this sequence being defined by the phase command.
 15. Themethod of claim 12 wherein capturing the digital signals responsive tothe clock signal comprises capturing the digital signals responsive tothe rising and falling edges of the clock signal.
 16. A readsynchronization circuit that adaptively adjusts respective timingoffsets of a plurality of digital signals applied on respective signalterminals and an external data clock signal to enable an external deviceto latch the digital signals responsive to the external data clocksignal, the read synchronization circuit comprising: a plurality oflatch circuits, each latch circuit including an input, an output coupledto a respective signal terminal, and a clock terminal, and each latchcircuit storing a signal applied on the input and providing the storedsignal on the signal terminal responsive to a clock signal applied onthe clock terminal; a plurality of phase command registers, each phasecommand register storing a phase command and each register beingassociated with at least one of the latch circuits; a clock generationcircuit coupled to latch circuits and the phase command registers, theclock generation circuit generating a plurality of internal clocksignals and the external data clock signal responsive to a read clocksignal, each internal clock signal and the external clock signal havinga respective phase shift relative to the read clock signal, and theclock generation circuit selecting one of the internal clock signals foreach latch circuit in response to the associated phase command andapplying the selected internal clock signal to the clock terminal of thelatch circuit to place digital signals on the corresponding signalterminal with a timing offset determined by the phase shift of theselected internal clock signal; and a control circuit coupled to theclock generation circuit and the phase command registers, the controlcircuit operable in response to a synchronization command to applysynchronization digital signals on the inputs of the latch circuits andto adjust the respective timing offsets between the external data clocksignal and the synchronization digital signals output by each latchcircuit by adjusting the respective values of the phase commands, andstoring final phase commands in each phase command register that allowthe synchronization digital signals to be successfully capturedresponsive to the external data clock signal.
 17. The readsynchronization circuit of claim 16 wherein the control circuitcomprises: a read data pattern generator that generates thesynchronization digital signals, each signal being a repeatingpseudo-random bit sequence; a command buffer and address capture circuitadapted to latch and output command-address signals applied on a commandaddress bus; a command decoder and sequencer coupled to the output ofthe command buffer and address capture circuit that generates aplurality of control signals responsive to the latched command-addresssignals, and generates a phase adjustment command word responsive toadjustment signals included in the latched command-address signals, thephase adjustment command word including information identifying aparticular digital signal; and an up/down phase counter-controllercoupled to the command decoder and sequencer to receive the phaseadjustment command word, and coupled to the phase command registers, thecounter-controller adjusting the value of the phase command stored inthe register associated with the identified digital signal responsive tothe phase adjustment command word.
 18. The read synchronization circuitof claim 17 wherein the counter-controller adjusts the value of thephase command stored in each register by first reading a present valueof the stored phase command, incrementing or decrementing the presentvalue of the phase command responsive to the phase adjustment command todevelop a new phase command word, and thereafter storing the new phasecommand in the register.
 19. The read synchronization circuit of claim16 wherein the clock generation circuit comprises: a programmable delayclock generator that generates N internal clock signals responsive tothe read clock signal; and a plurality of multiplexers, each multiplexerhaving an output coupled to a respective clock terminal of acorresponding latch circuit, a plurality of selection inputs coupled tothe associated phase command register to receive the stored phasecommand, and having N inputs coupled the programmable delay clockgenerator to receive the N internal clock signals, each multiplexerapplying a selected one of the N internal clock signals to the clockterminal of the corresponding latch responsive to the phase command. 20.The read synchronization circuit of claim 19 wherein the programmabledelay clock generator comprises a delay-locked loop circuit.
 21. Theread synchronization circuit of claim 16 wherein each latch circuitcomprises a data latch and a buffer.
 22. A memory device, comprising: atleast one array of memory cells adapted to store data at a locationdetermined by a row address and a column address; a control circuitadapted to receive external control signals and operable in response tothe external control signals to generate a plurality of internal controlsignals; a row address circuit adapted to receive and decode the rowaddress, and select a row of memory cells corresponding to the rowaddress responsive to the internal control signals; a column addresscircuit adapted to receive or apply data to at least one of the memorycells in the selected row corresponding to the column address responsiveto the internal control signals; a write data path circuit adapted tocouple data between a data bus and the column address circuit responsiveto the internal control signals; and a read data path circuit adapted tocouple data between the data bus and the column address circuitresponsive to the internal control signals, the read data path circuitcomprising a read synchronization circuit that adaptively adjustsrespective timing offsets of a plurality of digital signals applied onrespective signal terminals and an external data clock signal to enablean external device to latch the digital signals responsive to theexternal data clock signal, the read synchronization circuit comprising:a plurality of latch circuits, each latch circuit including an input, anoutput coupled to a respective signal terminal, and a clock terminal,and each latch circuit storing a signal applied on the input andproviding the stored signal on the signal terminal responsive to a clocksignal applied on the clock terminal; a plurality of phase commandregisters, each phase command register storing a phase commandresponsive to a control signal and each register being associated withat least one of the latch circuits; a clock generation circuit coupledto latch circuits and the phase command registers, the clock generationcircuit generating a plurality of internal clock signals and theexternal data clock signal responsive to a read clock signal, eachinternal clock signal and the external clock signal having a respectivephase shift relative to the read clock signal, and the clock generationcircuit selecting one of the internal clock signals for each latchcircuit in response to the associated phase command and applying theselected internal clock signal to the clock terminal of the latchcircuit to place digital signals on the corresponding signal terminalwith a timing offset determined by the phase shift of the selectedinternal clock signal; and a synchronization control circuit coupled tothe clock generation circuit and the phase command registers, thecontrol circuit operable in response to the initialization signals toapply synchronization digital signals on the inputs of the latchcircuits and to adjust the respective timing offsets between theexternal data clock signal and the synchronization digital signalsoutput by each latch circuit by adjusting the respective values of thephase commands, and storing final phase commands in each phase commandregister that allow the synchronization digital signals to besuccessfully captured responsive to the external data clock signal. 23.The memory device of claim 22 wherein the control circuit comprises: aread data pattern generator that generates the synchronization digitalsignals, each bit having a repeating 15 bit pseudo-random bit sequencefor the synchronization signals; a command buffer and address capturecircuit adapted to latch and output command-address signals applied on acommand address bus; a command decoder and sequencer coupled to theoutput of the command buffer and address capture circuit that generatesa plurality of control signals responsive to the latched command-addresssignals, and generates a phase adjustment command word responsive toadjustment signals included in the latched command-address signals, thephase adjustment command word including information identifying aparticular digital signal; and an up/down phase counter-controllercoupled to the command decoder and sequencer to receive the phaseadjustment command word, and coupled to the phase command registers, thecounter-controller adjusting the value of the phase command stored inthe register associated with the identified digital signal responsive tothe phase adjustment command word.
 24. The memory device of claim 23wherein the counter-controller adjusts the value of the phase commandstored in each register by first reading a present value of the storedphase command, incrementing or decrementing the present value of thephase command responsive to the phase adjustment command to develop anew phase command word, and thereafter storing the new phase command inthe register.
 25. The memory device of claim 22 wherein the clockgeneration circuit comprises: a programmable delay clock generator thatgenerates N internal clock signals responsive to the read clock signal;and a plurality of multiplexers, each multiplexer having an outputcoupled to a respective clock terminal of a corresponding latch circuit,a plurality of selection inputs coupled to the associated phase commandregister to receive the stored phase command, and having N inputscoupled the programmable delay clock generator to receive the N internalclock signals, each multiplexer applying a selected one of the Ninternal clock signals to the clock terminal of the corresponding latchresponsive to the phase command.
 26. The memory device of claim 25wherein the programmable delay clock generator comprises a delay-lockedloop circuit.
 27. The memory device of claim 22 wherein each latchcircuit comprises a data latch and a buffer.
 28. The memory device ofclaim 22 wherein the memory device comprises a packetized dynamic randomaccess memory device.
 29. The memory device of claim 28 wherein thepacketized dynamic random access memory device comprises an SLDRAM. 30.A memory system, comprising: a memory device, comprising, at least onearray of memory cells adapted to store data at a location determined bya row address and a column address; a control circuit adapted to receiveexternal control signals and operable in response to the externalcontrol signals to generate a plurality of internal control signals; arow address circuit adapted to receive and decode the row address, andselect a row of memory cells corresponding to the row address responsiveto the internal control signals; a column address circuit adapted toreceive or apply data to at least one of the memory cells in theselected row corresponding to the column address responsive to theinternal control signals; a write data path circuit adapted to coupledata between a data bus and the column address circuit responsive to theinternal control signals; and a read data path circuit adapted to coupledata between the data bus and the column address circuit responsive tothe internal control signals, the read data path circuit comprising aread synchronization circuit that adaptively adjusts respective timingoffsets of a plurality of digital signals applied on respective signalterminals and an external data clock signal to enable an external deviceto latch the digital signals responsive to the external data clocksignal, the read synchronization circuit comprising: a plurality oflatch circuits, each latch circuit including an input, an output coupledto a respective signal terminal, and a clock terminal, and each latchcircuit storing a signal applied on the input and providing the storedsignal on the signal terminal responsive to a clock signal applied onthe clock terminal; a plurality of phase command registers, each phasecommand register storing a phase command responsive to a control signaland each register being associated with at least one of the latchcircuits; a clock generation circuit coupled to latch circuits and thephase command registers, the clock generation circuit generating aplurality of internal clock signals and the external data clock signalresponsive to a read clock signal, each internal clock signal and theexternal clock signal having a respective phase shift relative to theread clock signal, and the clock generation circuit selecting one of theinternal clock signals for each latch circuit in response to theassociated phase command and applying the selected internal clock signalto the clock terminal of the latch circuit to place digital signals onthe corresponding signal terminal with a timing offset determined by thephase shift of the selected internal clock signal; and a synchronizationcontrol circuit coupled to the clock generation circuit and the phasecommand registers, the control circuit operable in response to theinternal control signals to apply synchronization digital signals on theinputs of the latch circuits and to adjust the respective timing offsetsbetween the external data clock signal and the synchronization digitalsignals output by each latch circuit by adjusting the respective valuesof the phase commands, and storing final phase commands in each phasecommand register that allow the synchronization digital signals to besuccessfully captured responsive to the external data clock signal; anda memory controller coupled to the memory device.
 31. The memory systemof claim 30 wherein the clock generation circuit comprises: aprogrammable delay clock generator that generates N internal clocksignals responsive to the read clock signal; and a plurality ofmultiplexers, each multiplexer having an output coupled to a respectiveclock terminal of a corresponding latch circuit, a plurality ofselection inputs coupled to the associated phase command register toreceive the stored phase command, and having N inputs coupled theprogrammable delay clock generator to receive the N internal clocksignals, each multiplexer applying a selected one of the N internalclock signals to the clock terminal of the corresponding latchresponsive to the phase command.
 32. The memory system of claim 31wherein the programmable delay clock generator comprises a delay-lockedloop circuit.
 33. The memory system of claim 30 wherein each latchcircuit comprises a data latch and a buffer.
 34. The memory system ofclaim 30 wherein the memory device comprises a packetized dynamic randomaccess memory device.
 35. The memory system of claim 34 wherein thepacketized dynamic random access memory device comprises an SLDRAM. 36.The memory system of claim 30 wherein the memory device comprises adouble-data rate memory device and the external data clock signalcomprises a data strobe signal DQS.
 37. An integrated circuit adapted toreceive a plurality of input signals and generate a plurality of outputsignals on respective, externally accessible terminals, comprising: acircuit adapted to receive a plurality of input signals applied torespective other of the terminals and to generate a plurality of outputsignals on respective other of the terminals; a read synchronizationcircuit that adaptively adjusts respective timing offsets of a pluralityof digital signals applied on respective signal terminals and anexternal data clock signal to enable an external device to latch thedigital signals responsive to the external data clock signal, the readsynchronization circuit comprising: a plurality of latch circuits, eachlatch circuit including an input, an output coupled to a respectivesignal terminal, and a clock terminal, and each latch circuit storing asignal applied on the input and providing the stored signal on thesignal terminal responsive to a clock signal applied on the clockterminal; a plurality of phase command registers, each phase commandregister storing a phase command responsive to a control signal and eachregister being associated with at least one of the latch circuits; aclock generation circuit coupled to latch circuits and the phase commandregisters, the clock generation circuit generating a plurality ofinternal clock signals and the external data clock signal responsive toa read clock signal, each internal clock signal and the external clocksignal having a respective phase shift relative to the read clocksignal, and the clock generation circuit selecting one of the internalclock signals for each latch circuit in response to the associated phasecommand and applying the selected internal clock signal to the clockterminal of the latch circuit to place digital signals on thecorresponding signal terminal with a timing offset determined by thephase shift of the selected internal clock signal; and a control circuitcoupled to the clock generation circuit and the phase command registers,the control circuit operable in response to a synchronization command toapply synchronization digital signals on the inputs of the latchcircuits and to adjust the respective timing offsets between theexternal data clock signal and the synchronization digital signalsoutput by each latch circuit by adjusting the respective values of thephase commands, and storing final phase commands in each phase commandregister that allow the synchronization digital signals to besuccessfully captured responsive to the external data clock signal. 38.The integrated circuit of claim 37 wherein the control circuitcomprises: a read data pattern generator that generates thesynchronization digital signals, each bit having a repeating 15 bitpseudo-random bit sequence for the synchronization digital signals; acommand buffer and address capture circuit adapted to latch and outputcommand-address signals applied on a command address bus; a commanddecoder and sequencer coupled to the output of the command buffer andaddress capture circuit that generates a plurality of control signalsresponsive to the latched command-address signals, and generates a phaseadjustment command word responsive to adjustment signals included in thelatched command-address signals, the phase adjustment command wordincluding information identifying a particular digital signal; and anup/down phase counter-controller coupled to the command decoder andsequencer to receive the phase adjustment command word, and coupled tothe phase command registers, the counter-controller adjusting the valueof the phase command stored in the register associated with theidentified digital signal responsive to the phase adjustment commandword.
 39. The integrated circuit of claim 38 wherein thecounter-controller adjusts the value of the phase command stored in eachregister by first reading a present value of the stored phase command,incrementing or decrementing the present value of the phase commandresponsive to the phase adjustment command to develop a new phasecommand word, and thereafter storing the new phase command in theregister.
 40. The integrated circuit of claim 37 wherein the clockgeneration circuit comprises: a programmable delay clock generator thatgenerates N internal clock signals responsive to the read clock signal;and a plurality of multiplexers, each multiplexer having an outputcoupled to a respective clock terminal of a corresponding latch circuit,a plurality of selection inputs coupled to the associated phase commandregister to receive the stored phase command, and having N inputscoupled the programmable delay clock generator to receive the N internalclock signals, each multiplexer applying a selected one of the Ninternal clock signals to the clock terminal of the corresponding latchresponsive to the phase command.
 41. The integrated circuit of claim 40wherein the programmable delay clock generator comprises a delay-lockedloop circuit.
 42. The integrated circuit of claim 37 wherein each latchcircuit comprises a data latch and a buffer.
 43. A computer system,comprising: a processor having a processor bus; an input device coupledto the processor through the processor bus adapted to allow data to beentered into the computer system; an output device coupled to theprocessor through the processor bus adapted to allow data to be outputfrom the computer system; and a memory device coupled to the processor,comprising, at least one array of memory cells adapted to store data ata location determined by a row address and a column address; a controlcircuit adapted to receive external control signals and operable inresponse to the external control signals to generate a plurality ofinternal control signals; a row address circuit adapted to receive anddecode the row address, and select a row of memory cells correspondingto the row address responsive to the internal control signals; a columnaddress circuit adapted to receive or apply data to at least one of thememory cells in the selected row corresponding to the column addressresponsive to the internal control signals; a write data path circuitadapted to couple data between a data bus and the column address circuitresponsive to the internal control signals; and a read data path circuitadapted to couple data between the data bus and the column addresscircuit responsive to the internal control signals, the read data pathcircuit comprising a read synchronization circuit that adaptivelyadjusts respective timing offsets of a plurality of digital signalsapplied on respective signal terminals and an external data clock signalto enable an external device to latch the digital signals responsive tothe external data clock signal, the read synchronization circuitcomprising: a plurality of latch circuits, each latch circuit includingan input, an output coupled to a respective signal terminal, and a clockterminal, and each latch circuit storing a signal applied on the inputand providing the stored signal on the signal terminal responsive to aclock signal applied on the clock terminal; a plurality of phase commandregisters, each phase command register storing a phase commandresponsive to a control signal and each register being associated withat least one of the latch circuits; a clock generation circuit coupledto latch circuits and the phase command registers, the clock generationcircuit generating a plurality of internal clock signals and theexternal data clock signal responsive to a read clock signal, eachinternal clock signal and the external clock signal having a respectivephase shift relative to the read clock signal, and the clock generationcircuit selecting one of the internal clock signals for each latchcircuit in response to the associated phase command and applying theselected internal clock signal to the clock terminal of the latchcircuit to place digital signals on the corresponding signal terminalwith a timing offset determined by the phase shift of the selectedinternal clock signal; and a synchronization control circuit coupled tothe clock generation circuit and the phase command registers, thecontrol circuit operable in response to the internal control signals toapply synchronization digital signals on the inputs of the latchcircuits and to adjust the respective timing offsets between theexternal data clock signal and the synchronization digital signalsoutput by each latch circuit by adjusting the respective values of thephase commands, and storing final phase commands in each phase commandregister that allow the synchronization digital signals to besuccessfully captured responsive to the external data clock signal. 44.The computer system of claim 43 wherein the clock generation circuitcomprises: a programmable delay clock generator that generates Ninternal clock signals responsive to the read clock signal; and aplurality of multiplexers, each multiplexer having an output coupled toa respective clock terminal of a corresponding latch circuit, aplurality of selection inputs coupled to the associated phase commandregister to receive the stored phase command, and having N inputscoupled the programmable delay clock generator to receive the N internalclock signals, each multiplexer applying a selected one of the Ninternal clock signals to the clock terminal of the corresponding latchresponsive to the phase command.
 45. The computer system of claim 44wherein the programmable delay clock generator comprises a delay-lockedloop circuit.
 46. The computer system of claim 43 wherein each latchcircuit comprises a data latch and a buffer.
 47. The computer system ofclaim 43 wherein the memory device comprises a packetized dynamic randomaccess memory device.
 48. The computer system of claim 47 wherein thepacketized dynamic random access memory device comprises an SLDRAM. 49.The computer system of claim 43 wherein the memory device comprises adouble-data rate memory device and the external data clock signalcomprises a data strobe signal DQS.
 50. A read synchronization circuitthat adaptively adjusts respective timing offsets of a plurality ofdigital signals applied on respective signal terminals and an externaldata clock signal to enable an external device to latch the digitalsignals responsive to the external data clock signal, the readsynchronization circuit comprising: a plurality of latch circuits, eachlatch circuit including an input, an output coupled to a respectivesignal terminal, and a clock terminal, and each latch circuit storing asignal applied on the input and providing the stored signal on thesignal terminal responsive to a clock signal applied on the clockterminal; a plurality of phase command registers, each phase commandregister storing a phase command and each register being associated withone of the latch circuits; a programmable delay clock generator thatdevelops N internal clock signals responsive to the read clock signal; aplurality of multiplexers, each multiplexer having an output coupled toa respective clock terminal of a corresponding latch circuit, aplurality of selection inputs coupled to an associated phase commandregister to receive the stored phase command, and N inputs coupled tothe generator to receive the N internal clocks signals, respectively,the multiplexer applying a selected internal clock signal on the outputto clock the corresponding latch circuit in response to the phasecommand; a read data pattern generator coupled to the inputs of thelatch circuits, the generator applying a synchronization signal to eachinput; and an up/down phase counter-controller coupled to the read datapattern generator and the phase command registers, thecounter-controller operable to adjust the values of the phase commandsstored in the registers in response to received phase adjustment commandwords to thereby adjust the respective timing offsets between theexternal data clock signal and the synchronization signal being outputby the latch circuits, and the counter-controller storing final phasecommands in each phase command register that allow the synchronizationdigital signals to be successfully captured responsive to the externaldata clock signal.
 51. The read synchronization circuit of claim 50wherein the counter-controller adjusts the value of the phase commandstored in each register by first reading a present value of the storedphase command, incrementing or decrementing the present value of thephase command responsive to the phase adjustment command to develop anew phase command word, and thereafter storing the new phase command inthe register.
 52. The read synchronization circuit of claim 50 whereinthe programmable delay clock generator comprises a delay-locked loopcircuit.
 53. The read synchronization circuit of claim 50 wherein eachlatch circuit comprises a data latch and a buffer.
 54. A readsynchronization circuit that adaptively adjusts respective timingoffsets of a plurality of digital signals applied on respective signalterminals and an external data clock signal to enable an external deviceto latch the digital signals responsive to the external data clocksignal, the read synchronization circuit comprising: a plurality of datastorage means for storing respective signals and providing the storedsignals on respective signal terminals, each data storage means storingthe signal applied on an input and providing the stored signal on thecorresponding signal terminal responsive to a clock signal; a pluralityof phase storage means for storing respective phase commands, each phasestorage means being associated with one of the data storage means; aclock generation means coupled to the data storage means and the phasestorage means for generating a plurality of internal clock signals andthe external data clock signal responsive to a read clock signal, eachinternal clock signal and the external clock signal having a respectivephase shift relative to the read clock signal, and the clock generationmeans including selection means for selecting one of the internal clocksignals for each data storage means in response to the associated phasecommand and applying the selected internal clock signal as the clocksignal to the data storage means to place digital signals on thecorresponding signal terminal with a timing offset determined by thephase shift of the selected internal clock signal; and a control meanscoupled to the clock generation means and the phase storage means forreceiving a synchronization command and, in response to thesynchronization command, applying a respective synchronization digitalsignals to each storage means and adjusting the respective timingoffsets between the external data clock signal and each of thesynchronization digital signals being provided on the signal terminalsby each storage means by adjusting the respective values of the phasecommands stored in the phase storage means, and storing final phasecommands in each phase storage means that allow the synchronizationdigital signals to be successfully captured responsive to the externaldata clock signal.
 55. The read synchronization circuit of claim 54wherein the control means comprises: a data pattern generation means forgenerating the synchronization digital signals, each signal being arepeating pseudo-random bit sequence; a command buffering and addresscapturing means for latching command-address signals applied on acommand address bus; a command decoding and sequencing means coupled tothe command buffering and address capturing means for generating aplurality of control signals responsive to the latched command-addresssignals, and generating a phase adjustment command word responsive toadjustment signals included in the latched command-address signals, thephase adjustment command word including information identifying aparticular digital signal; and a phase counter-controller means coupledto the command decoding and sequencing means to receive the phaseadjustment command word and coupled to the phase storage means, thecounter-controller means adjusting the value of the phase command storedin the phase storage means associated with the identified digital signalresponsive to the phase adjustment command word.
 56. The readsynchronization circuit of claim 55 wherein the counter-controller meansadjusts the value of the phase command stored in each phase storagemeans by first reading a present value of the stored phase command,incrementing or decrementing the present value of the phase commandresponsive to the phase adjustment command to develop a new phasecommand word, and thereafter storing the new phase command in the phasestorage means.
 57. The read synchronization circuit of claim 54 whereinthe clock generation means comprises: a programmable delay clockgeneration means for generating N internal clock signals responsive tothe read clock signal; and a plurality of multiplexing means, eachmultiplexing means having an output coupled to a corresponding datastorage means to apply the clock signal to the storage means andincluding a plurality of selection inputs coupled to the associatedphase storage means to receive the stored phase command, and having Ninputs coupled the programmable delay clock generation means to receivethe N internal clock signals, each multiplexing means applying aselected one of the N internal clock signals to the clock terminal ofthe corresponding data storage means responsive to the phase command.58. The read synchronization circuit of claim 57 wherein theprogrammable delay clock generation means comprises a delay-locked loopmeans.
 59. The read synchronization circuit of claim 54 wherein eachdata storage means comprises a latching means for storing data and abuffer means coupled to the latching means for providing the stored dataon the corresponding signal terminal.
 60. A memory system, comprising: asystem clock generator that develops a system read data clock signal; amemory device coupled to the clock generator to receive the system readdata clock signal, comprising, at least one array of memory cellsadapted to store data at a location determined by a row address and acolumn address; a control circuit adapted to receive external controlsignals and operable in response to the external control signals togenerate a plurality of internal control signals; a row address circuitadapted to receive and decode the row address, and select a row ofmemory cells corresponding to the row address responsive to the internalcontrol signals; a column address circuit adapted to receive or applydata to at least one of the memory cells in the selected rowcorresponding to the column address responsive to the internal controlsignals; a write data path circuit adapted to couple data between a databus and the column address circuit responsive to the internal controlsignals; and a read data path circuit adapted to couple data between thedata bus and the column address circuit responsive to the internalcontrol signals, the read data path circuit comprising a readsynchronization circuit that adaptively adjusts respective timingoffsets of a plurality of digital signals applied on respective signalterminals and the system read data clock signal to enable an externaldevice to latch the digital signals responsive to the system read dataclock signal, the read synchronization circuit comprising: a pluralityof latch circuits, each latch circuit including an input, an outputcoupled to a respective signal terminal, and a clock terminal, and eachlatch circuit storing a signal applied on the input and providing thestored signal on the signal terminal responsive to a clock signalapplied on the clock terminal; a plurality of phase command registers,each phase command register storing a phase command responsive to acontrol signal and each register being associated with at least one ofthe latch circuits; an internal clock generation circuit coupled tolatch circuits and the phase command registers, the internal clockgeneration circuit generating a plurality of internal clock signalsresponsive to the system read data clock signal, each internal clocksignal and the system read data clock signal having a respective phaseshift relative to the system read data clock signal, and the internalclock generation circuit selecting one of the internal clock signals foreach latch circuit in response to the associated phase command andapplying the selected internal clock signal to the clock terminal of thelatch circuit to place digital signals on the corresponding signalterminal with a timing offset determined by the phase shift of theselected internal clock signal; and a synchronization control circuitcoupled to the internal clock generation circuit and the phase commandregisters, the control circuit operable in response to the internalcontrol signals to apply synchronization digital signals on the inputsof the latch circuits and to adjust the respective timing offsetsbetween the system read data clock signal and the synchronizationdigital signals output by each latch circuit by adjusting the respectivevalues of the phase commands, and storing final phase commands in eachphase command register that allow the synchronization digital signals tobe successfully captured responsive to the system read data clocksignal; and a memory controller coupled to the memory device and coupledto the system read clock generator to receive the system read data clocksignal.
 61. The memory system of claim 60 wherein the clock generationcircuit comprises: a programmable delay clock generator that generates Ninternal clock signals responsive to the read clock signal; and aplurality of multiplexers, each multiplexer having an output coupled toa respective clock terminal of a corresponding latch circuit, aplurality of selection inputs coupled to the associated phase commandregister to receive the stored phase command, and having N inputscoupled the programmable delay clock generator to receive the N internalclock signals, each multiplexer applying a selected one of the Ninternal clock signals to the clock terminal of the corresponding latchresponsive to the phase command.
 62. The memory system of claim 61wherein the programmable delay clock generator comprises a delay-lockedloop circuit.
 63. The memory system of claim 60 wherein each latchcircuit comprises a data latch and a buffer.
 64. The memory system ofclaim 60 wherein the memory device comprises a packetized dynamic randomaccess memory device.
 65. The memory system of claim 64 wherein thepacketized dynamic random access memory device comprises an SLDRAM. 66.The memory system of claim 60 wherein the memory device comprises adouble-data rate memory device and the external data clock signalcomprises a data strobe signal DQS.